In an active matrix flat screen, each image dot is addressed by means of a switching transistor. Each selection line of the matrix is thus connected to the gates of the switching transistors of a row of image dots. These lines are therefore strongly capacitive. On each video frame, they are each selected in sequence, one by one, in a direction of scanning of the lines of the screen, during a line selection time corresponding to a fraction of the duration of the frame, enabling the video voltages to be applied to the image dots of the row.
The selection of a line thus corresponds to the application, during the corresponding line selection time, of a predetermined voltage level which controls the passing state of the switching transistors of the corresponding row of image dots. Outside the line selection time, said line is held at a voltage level capable of holding the switching transistors of the active matrix in the blocked state. Vgon and Vgoff are usually used to denote the voltage levels to be applied to the line to make these transistors passing (Vgon) and blocked (Vgoff). These levels are determined according to characteristic video voltages.
The selection lines are usually controlled by circuits that include one or more shift registers in series, each having a plurality of cascaded stages, each stage being capable of switching the levels Vgon and Vgoff at the output to a corresponding line of the matrix, according to the sequencing of the selection of the lines.
It is well known in the field of flat screens to use thin-film field-effect transistors (TFT), both for the switching transistors in the active matrix, which enable a voltage to be applied to a pixel, and for the transistors of the shift registers of the control circuits of the selection lines of this matrix.
One well-known problem encountered by the designers of such circuits is how to manage the drift in the threshold voltage of the thin-film transistors. This drift depends notably on the temperature conditions, but also on the voltage levels applied and on the current level conducted by these transistors. It conditions their lifespan.
Moreover, integrating the active matrix and the control circuits on one and the same substrate is advantageous. However, it presupposes that the control circuits take little space, above all when the matrix contains a large number of pixels.
Line control circuits have been designed to meet these various needs. In particular, the Patent Application EP 0815 562 discloses a shift register structure with a small number of field-effect transistors, of the same polarity and with a small footprint. This structure leads to a low duty cycle for the transistors, and is also designed to limit the voltage levels that are applied to them. In particular, when a stage is not active, its transistors have their gate-source voltage below or equal to zero. These transistor control conditions make it possible to improve their lifespan.
More specifically, this structure is based on the use, in each stage of an output transistor able to conduct a sufficient current to charge the output capacitive line, associated with a “bootstrap” capacitor, connected between its gate and its source. The drain of the output transistor receives a clock signal; its source forms the output node on a line of the active matrix; its gate is controlled by the bias of a precharging transistor, which brings the gate to a precharging potential making it possible to control the passing state of the output transistor at the input in the line selection phase. In the selection phase, the gate of the output transistor then follows the potential of its source via the bootstrap capacitor, which holds the transistor in the passing state throughout the line selection phase. The gate precharging potential is determined so that the output transistor conducts an output current of sufficient level to transfer a pulse of the clock signal applied to its drain, to its source which forms the output node. The gate of the output transistor is also controlled by a discharge transistor activated after the line selection phase, to bring the gate of the output transistor to a voltage level enabling it to be blocked.
Although this structure is advantageous in that it requires only a small number of transistors, controlled with a low duty cycle and low voltage levels, optimized with respect to the levels Vgon and Vgoff to be applied to the output, it does, however, exhibit a sensitivity to the drift in the threshold voltage of the output transistor, which limits its lifespan.
In practice, it has been seen that, in the selection phase, the gate potential increases with the source potential, by bootstrap effect from the capacitor connected between the gate and the source. If V1 is used to denote the precharging potential of the gate at the input in the selection phase, the gate potential then increases by a quantity Va proportional to the voltage at the output node Vgon. The gate-source voltage Vgs seen by the output transistors during each line selection phase is thus greater than the threshold voltage of the transistor. Over time, it induces a drift in the threshold voltage, which can reach ten or so volts. Because of the drift, there comes a time when the precharged voltage level V1 on the gate is no longer sufficient to make an output transistor passing, or at least sufficiently conductive to charge the capacitor of the output node or of the line. This moment marks the end of life of the shift register.
Also, depending on the lifespan desired for the control circuit, in line with the lifespan of the active matrix with which it is to be integrated, there is a need to define a precharging voltage level V1 that is greater than the precharging voltage level that would be necessary, and sufficient, at the start of life of the output transistor, to simply charge the capacitor of the line.
In practice, the precharging voltage level V1 applied by the precharging transistor is equal to the level Vgon supplied by the output node of the preceding stage, during the associated line selection time, minus the threshold voltage of the precharging transistor. Thus, it is the level Vgon that has to be overevaluated, according to the lifespan sought, to take account of the drift over time of the threshold voltage of the output transistors.
For example, a transistor whose threshold voltage at the start of life is of the order of 1 or 2 volts, can have its threshold voltage drift by approximately 13 volts. In this case, a voltage Vgon of the order of 20 volts can be chosen, whereas at the start of life, a voltage Vgon of the order of 7 volts would have been sufficient. This means that, at the start of life, the output transistor is then extremely conductive. The excessive output current tends to accelerate the speed with which the threshold voltage of the output transistor will drift. Its lifespan is hence diminished.
For each target application or product, the design of such a register must thus take account of three criteria:                The minimum current level that the control transistor must be capable of supplying to charge the output line. This will depend notably on the type of screen involved, in particular on the number of image dots per line and the technology used. This minimum current level defines the end of life of the transistor: starting from the first time the product (i.e. the screen) is started up, the end of life is marked by the moment when the output transistor will no longer be capable of supplying this minimum current.        The speed of drift of the threshold voltage of the output transistor, which is a function of the voltage level applied to its gate, and its technology.        The maximum level Vgon that can be applied to the control circuit, which is a function of the screen controller concerned.        